In integrated circuit design methodology, timing closure is a process that involves analyzing each path in the circuit to determine whether it meets the clock cycle time requirements of the design. A “path” in a circuit design refers to an electrical signal path (i.e., the series of interconnects and devices) between two nodes in the design. A “critical path” is the path between two nodes in a design having the maximum delay. If a path does not meet the clock cycle time requirements, the operational speed of one or more components on the path can typically be improved. The operational speed of a path component can be improved in many ways. A typical approach for improving the speed of a path component involves replacing a higher threshold voltage implementation of the path component with a lower threshold voltage implementation of the component, which operates faster. However, each design change has trade-offs in terms of various circuit operation parameters. For example, a higher threshold voltage implementation of the path component can be replaced with a lower threshold voltage implementation of the component, but lower threshold voltage implementations leak more power than the higher threshold voltage implementations. As a result, such a replacement generally will increase the power requirements in the circuit. After design changes are made to the circuit, all paths are again analyzed to determine whether they meet the clock cycle time requirements of the design.
Timing of integrated circuits may vary due to the effects of environmental and process variation. Example sources of variation include: voltage, metal thickness, temperature, transistor channel length, transistor threshold voltage, gate oxide thickness and other process controlled performance changing parameters. Timing analyses are typically performed based on a discrete set of defined parameters relating to the environmental and process parameters. For example, a timing analysis can be performed based on a set of parameters that define nominal values of these parameters. Other analyses can be performed based on best case and worst case values of the design parameters to ensure that timing is met for the full range of expected operating and process conditions. A defined set of environmental and process parameters against which a timing analysis is run is called a “corner.”
Energy consumption of an integrated circuit is exponentially related to the supply voltage of the chip. Reducing the supply voltage of the circuit is the most effective way to reduce its energy consumption. Voltage scaling is a technique by which supply voltage is reduced based on various factors, such as peak computing requirements versus average computing requirements. High performance is typically needed only a small fraction of the time, while for the rest of the time, a low-performance, low-power processor would suffice. Low performance can be achieved by lowering the supply voltage of the integrated circuit, which in turn will reduce the operating frequency of the processor when the high performance is not needed.
Adaptive voltage scaling (AVS) is a power management technique in which the supply voltage of an integrated circuit is adjusted automatically. The supply voltage is adjusted using closed loop feedback to a minimum level that is required for the proper operation of the integrated circuit at a given clock frequency. AVS uses a closed loop approach to regulate processor performance by automatically adjusting the power supply voltage of the integrated circuit power supply to compensate for process and temperature variation in the processor. Thus, the supply voltage in the AVS system is automatically reduced at lower temperatures or other conditions where the integrated circuit does not need as much performance, and for chips that come out the manufacturing process with a faster speed. As the supply voltage is reduced, the power consumption is also reduced. It would be advantageous for an AVS system to work effectively if timing closure is achieved over a sufficiently wide voltage range, and circuit performance sensitivity to voltage was made consistent across all critical paths on the chip.